It performs bit by bit logical operation on the vector operand and returns a boolean value.įor example, &(1011) = 1 & 0 & 1 & 1 = 0 // reduction and of 1011

This operand is useful for converting a multi-bit vector into a single bit scalar value. Unlike logical and bitwise logical operators, the Reduction operator is a unary operator. $display (“X & Z = %b“, X & Z) // Bitwise AND $display (“X ^~ Y = %b“, X ^~ Y) // Bitwise XNOR $display (“X ^ Y = %b“, X ^ Y) // Bitwise XOR $display (“X | Y = %b“, X | Y) // Bitwise OR $display (“X & Y = %b“, X & Y) // Bitwise AND We will get a better understanding when we go through the simulated output of this code. Bitwise AND is similar to concatenating a & b and a & b which gives a result 00. Check out the example below.įor example: bitwise AND of a = 3(11) and b=2 (00). If one of the operands is shorter than the other, the length will be made the same by adding zeros on the shorter operand. They take each bit in one operand and perform the operation with the corresponding bit in the other operand. This operator is a bit of an odd cross between a logical operator and an arithmetic operator. Verilog supports the use of a bit-wise operator. $display(“out = %b“, (A=2)&(B=3) // Evaluates 1 if both A=2 and B=3 are true otherwise false. $display(“logical_AND(din1,din2) = %b“, din1 &din2) // Equivalent to ( x & logical-1) $display(“logical_NOT(B) = %b“, !B) // Equivalent to not(logical-0) $display(“logical_NOT(A) = %b“, !A) // Equivalent to not(logical-1) $display(“logical_OR(A,B)= %b“, A ||B) // Equivalent to logical-1 || logical-0 $display(“logical_AND(A,B)=%b”, A &B) // Equivalent to logical-1 & logical-0 Here’s how Verilog performs logical operations.

Will convert to zero if A is non-zero or 1 A is zero or false value The result will be true if either A or B is true The result will be 1 (true ) if A and B are true These are the logical operators available in Verilog. Therefore, AND of true and false will give you false (0). Hence, Logical value of 3 is true(1) and for 0, it is false(0). Let’s say we have to perform logical and operation between 3 (non-zero) and 0 (zero). Logical operators perform a logical operation on the logical value of the operands and tell you whether it is true or false, i.e., it returns a boolean value. $display ('modulus(data1,data2) = %d', data1 % data2) $display ('divide(data1,data2) = %d', data1 / data2) $display ('multiply(data1,data2) = %d', data1 * data2) $display ('subtract(data1,data2) = %d', data1 - data2) module arithmetic_operations ĭata2 = 9 $display ('add(data1,data2) = %d', data1 + data2) Now that we have an idea of what arithmetic operators are, we can see how they are used in Verilog using a sample program as an example. 32'd10/5 // will yield incorrect result Since Verilog converts negative numbers into 2’s complement internally, writing in ' format will yield incorrect result. You can refer to LRM 20.9 for more information.Note: It is advisable to write negative numbers in real or integer format. The more general form of this function is $countbits, which you can used to count 0, 1, x, or z in a bit vector. SystemVerilog has $countones to count number of ones in a bit vector. SystemVerilog builtin function $countones.If we do a loop, we can unset all the set bits, and count the number of the set bits as well. If we subtract 1 from the original number and do bitwise with itself, we will unset the rightmost set bit. The idea is to subtract 1 from the original number, and this toggles to the rightmost set bit. It’s somewhat about bit manipulation too. We are using while loop here, and the condition is valid only when the number is still positive, which means until its highest bit. After each iteration, the number is shifted 1 bit to the right. So, the basic the idea is to only add 1 to the result when the last bit is 1, which can be accomplished by using a mask of number 1. Loop through the number and use bit comparison at the last bit.

Verilog bit count